Title: High-Speed Wireline Transceivers for Backplane Communications
Place: École Polytechnique de Montréal
Date and time: 19/09/2013

 

Abstract

This presentation describes the design of fully-adaptive multi-standard wireline transceivers targeted for high-speed communication over lossy channels such as backplanes. Architectural solutions resolving channel-induced signal distortions along with adaptation techniques for reliable operation across various channels are introduced. Hybrid clocking circuits for wide-range operation using a combination of ring and LC PLLs are proposed. Finally, the implementation of these techniques in two fully-adaptive transceivers in 28nm CMOS operating up to 12.5Gb/s and 13.1Gb/s is discussed.

 

Biography

Jafar Savoj received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1996, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, in 1998 and 2001, respectively.

Dr. Savoj’s areas of expertise include technology and product development for wireless, wireline, and analog systems. He is currently an Engineering Director with the Serdes Technology Group at Xilinx, San Jose, CA, and leads high-speed, low-power wireline transceiver development for FPGA applications. From 2008 to 2010, he was with Qualcomm, Santa Clara, CA, and led the advanced technology development group for wireless connectivity. He was responsible for development of WLAN and Near Field Communication (NFC) transceivers, and low power chip-to-chip interfaces for mobile platforms. From 2005 to 2008, he was a principal engineer at Rambus, where he developed ultra-high-speed data converters for software programmable wireline transceivers. Prior to that, he held design engineering positions at Marvell Semiconductor, Santa Clara, CA, focusing on fiber channel and Gigabit Ethernet transceivers; and at Transpectrum, Los Angeles, CA, architecting 10-Gb/s and 40-Gb/s optical transceivers in CMOS technology. He held a lecturing position at Stanford University in 2004. He is the author of High-Speed CMOS Circuits for Optical Receivers (Kluwer, 2001).

Dr. Savoj was a recipient of the IEEE Solid-State Circuits Society (SSCS) Predoctoral Fellowship for 2000–2001, and the Beatrice Winner Award for Editorial Excellence at the 2001 ISSCC, and the Design Contest Award of the 2001 Design Automation Conference. He is a SSCS Distinguished Lecturer and a technical program committee member of ISSCC (Analog Subcommittee). He served as a technical program committee member of the IEEE Custom Integrated Circuits Conference (CICC) from 2001 to 2007 and the IEEE Symposium on VLSI Circuits from 2007 to 2011. He was an Associate Editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 2008 to 2011 and a Guest Editor for the Journal in 2005, 2006 and 2011.