Yves_Leduc

 

Title: NAPA, A CYCLE BASED SIMULATOR FOR MIXED SIGNAL DESIGN

Place: École Polytechnique de Montréal, Main Building (Pavillon Principal), Room A-621
Date and time:  Friday Jan 10, 2014, 11:00-14:00

 

Biography:

Yves Leduc received his PhD in Electronic Engineering from the Catholic University of Louvain in 1979, joined Texas Instruments in 1980 and was elected TI Fellow in 1998. He currently holds the TI Chair at the University of Nice Sophia Antipolis (France). Dr. Leduc was one of the pioneers in mixed signal SOCs in CMOS technology for mobile applications. He developed key design methodologies and software solutions for complex mixed signal SOCs. He created the first integrated mixed signal IC interfaces with DSPs and contributed to the success of TI in the wireless telecommunication business. Dr. Leduc designed several digital modulation schemes which were the keystone of  he TI ‘Digital Radio Processors’, and the TI ‘Smart Reflex’ concept, introducing DVFS in a novel design methodology of large SOCs.

 

Abstract:

NAPA is a high level circuit and system simulator that was conceived to support the design of competitive high precision sigma-delta converters and extended to other mixed signal systems. NAPA is free and based on free and open softwares. It is currently running on Windows 7 – 64 bits, but its core, written in ANSI C99, is OS agnostic. As the main developer of NAPA, Yves Leduc got recently the authorization to modify, extend and distribute it for educational purposes. NAPA assists students to go deeper in the understanding of electronic circuits and assists professors to react quickly to the questions of the students and to illustrate the answers ‘in live’. Its remarkable speed, large extensibility and simplicity are particularly useful to address circuit design problems. NAPA was key for many years in the designs of mixed signal  IC’s of the wireless division of TI. NAPA is used for modeling and simulation of simple or complex mixed signal systems and  becomes naturally a repository of techniques and solutions developed by its users.

In the first part of the talk, the fundamentals of NAPA simulator will be presented, its comparative advantages and characteristics will be described. Simple examples will illustrate the concepts supporting the tool, and will show how easy it is to describe and to simulate a circuit with NAPA.

The second part will use a SWC integrator module to show how far high level modeling can predict accurately the behavior of such an integrator. From the most ideal models to the most complete one, we will use NAPA in live to discover the power, precision and the speed of this amazing tool. It will be the opportunity to see how useful it could be to help the design of mixed signal systems and assist the students, research engineers and professors in their daily work.

 

 

Sponsors:

-IEEE-SSCS Montreal Chapter

-Dept of Elec. Eng., Polytechnique Montreal

-ReSMiQ

 

Tentative Program:

11:00am to noon:  Lecture

noon to 1:00pm:  Software demo and talk on simulation techniques

1:00pm to 2:00 pm:  Lunch and Open discussion

 

Registration:

To register please send an e-mail include following information to Mrs. Marie-Yannick Laplante on marie-yannick.laplante@polymtl.ca by December 15th:

– Your Name

– The Institute, University and Department.

– Your IEEE Membership Number (if you are member) or Student ID (for students)

 

Notice:

We strongly recommend having your own laptops for more convenient during the simulation exercise session.

The Simulator can be downloaded via www.borogoves.eu

 

More Information:

For more information and for any question please do not hesitate to contact Ehsan Kamrani on ehsan.kamrani@ieee.org.